Rapid advances in VLSI technology and design techniques have enabled microcomputers to approach the performance and sophistication of a super minicomputer. As processors become faster, the traffic between the processor and off-chip main memory increases causing a performance bottleneck. In prior systems this bottleneck has been lessened by using a local on-chip memory (called a cache) to store frequently used memory data. If data required by the processor is in the cache, an off-chip memory reference is avoided since the data can be fetched directly from the cache. Further reductions in memory traffic could be achieved if the cache design were expanded to include instruction fetches. For example if information relating to call and return instructions were available locally on the chip, call and return instructions could execute without references to the off-chip memory. The resulting decreased memory bus traffic would also reduce the probability that a load or store instruction will have to wait for the memory bus.
It is therefore an object of the present invention to provide an apparatus for minimizing main memory references occurring during execution of call/return instructions.